1. Field of the Invention
This invention relates to semiconductor device manufacturing and particularly to the manufacturing of metallurgy for interconnecting elements in integrated circuit devices wherein particular efforts are directed to increasing the yield of semiconductor devices.
2. Background of the Invention
In the manufacture of semiconductor integrated circuit devices the metallurgy which interconnects semiconductor devices is of great importance. As circuit densities become greater the importance of low resistivity interconnects becomes critical. Recently, copper has begun to replace aluminum as the conductor of choice. Copper exhibits lower susceptibility to electromigration failure as compared to aluminum.
Because of the difficulty in defining fine lines in integrated circuit designs, the use of Chemical-Mechanical-Planarization (CMP) has become the process of choice by circuit manufacturers. CMP technology, as described in U.S. Pat. No. 4,789,648 to Chow et al. requires that a recess be formed in a dielectric layer, a conductor is deposited within the recess and its adjacent regions and the excess conductor is removed by a CMP process. Dual Damascene is described as the process in which an entire level of conductive metallurgy, lateral troughs and vertical vias, is formed using a single deposition followed by a single planarization step.
Despite the fact that copper-based metallurgy has certain advantages over aluminum-based metallurgy, copper has certain negative aspects which need to be dealt with in order to develop a manufacturable copper metallurgy process. One of the drawbacks of copper is its ability to diffuse rapidly through standard semiconductor insulators and into silicon causing xe2x80x9cpoisoningxe2x80x9d of pn junctions and failure of integrated circuits. To avoid this problem it is necessary to provide extensive diffusion barriers which entirely surround the copper conductors.
Another difficulty faced by copper-based metallurgy lies in the lack of a self-passivating oxide as found in aluminum-based metallurgy. Copper-based metallurgy cannot be exposed for extended periods of time to oxidizing atmospheres without jeopardizing the integrity of interconnections.
Metallurgy levels in semiconductor technology must meet two requirements, one, it must connect vertically between a semiconductor and another level of metal or between two different levels of metal and, two, it must interconnect two or more points in a plane laterally. The conductive portions of the metallurgy are normally formed in an matrix of dielectric insulator.
In the well known dual Damascene technology, both vertical (vias) and lateral (troughs) are defined sequentially in the intermetal insulator prior to the deposition or formation of any conductive layers. Techniques exist for via first and for trough first dual Damascene processing. Once the insulator has been patterned, copper can be formed by any preferable method such as chemical vapor deposition or electroplating. The amount of deposited copper is determined by that which can completely fill all of the vias and troughs. Since these deposition techniques are substantially conformal processes a certain amount of excess copper is formed which must be removed in order to delineate the metallurgy as isolated units.
The preferred process for removal of excess copper is that of Chemical-Mechanical Planarization or CMP as described in U.S. Pat. No. 4,789,648 to Chow et al., issued Dec. 6, 1988 and numerous subsequent references. CMP of metal layers requires a polishing tool and a slurry which is usually chemically reactive with the metal. The article xe2x80x9cChemical-mechanical polishing of copper with oxide and polymer interlevel dielectrics,xe2x80x9d R. J. Gutman et al., Thin Solid Films, Vol. 270, No. 1-2, Dec. 1, 1995, pp. 596-600 describes slurries for CMP of copper including nitric acid based slurries.
Although it is desirable to provide a coplanar metal conductor/insulator surface, CMP technology has two primary and competitive process detractors: dishing and erosion. Dishing is the phenomenon in which wide areas of polished copper are over polished creating a dish-like depression in the surface of the copper. Too much dishing causes failures in copper lines. Erosion is the phenomenon in which the intermetal dielectric is caused to be eroded allowing too much copper to be removed. Dishing is a function of line width while erosion is a function of the density of lines. In a typical semiconductor circuit the thickness of the conductive layers are on the order of a single micron or on the order of {fraction (1/70)}th of the thickness of ordinary paper.
As suggested in the above article, the addition of a film-forming organic reagent can be added to a slurry in order to protect the copper from the chemical environment of the slurry. Benzotriazole (BTA) is a known copper surface passivation agent. When BTA is added to an acid-based slurry, a non-native surface film is formed which inhibits the etching of copper in low lying regions. This surface film forms a passivating organic layer on the surface of the copper which keeps the copper from oxidizing.
It has been found in the manufacturing of dual Damascene copper metallurgy that certain known practices create problems in consistently providing high yield of product wafer particularly where frequent testing is required at intermediate levels of metallurgy. A significant number of failures have been observed by the inventors when attempts have been made to probe semiconductor chips polished in slurries using BTA as a passivating agent. While probe pressure was adequate to penetrate the passivation film is many cases, the number of failures attributed to high resistance two-point probes was unacceptable.
Accordingly, it is an object to increase the yield of processed wafers containing copper metallurgy.
It is another object of the invention to provide a process which is capable of easy integration into dual Damascene copper technology.
It is yet another object to improve the state of copper metallurgy manufacturing by providing a process which is easily implemented by any number of typically available tools of a semiconductor manufacturing line.
These and other objects are achieved by a simple annealing process which not only eliminates the non-native organic film formed by the presence of BTA in a slurry, but also reduces the amount of oxidation experienced by the exposed, unprotected areas of copper on semiconductor wafers without compromising the ability to probe wafers or to perform subsequent processing steps in a manufacturing environment.